Selector devices

ABSTRACT

Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.

BACKGROUND

A selector device is a two-terminal device exhibiting a volatile changein resistance. In an off state, a selector device may exhibit highresistance; in an on state, a selector device may exhibit lowresistance.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example, not by way oflimitation, in the figures of the accompanying drawings.

FIG. 1A is a perspective view of a portion of a memory array including aselector device, in accordance with various embodiments.

FIG. 1B is a schematic illustration of a memory cell of the memory arrayof FIG. 1A, in accordance with various embodiments.

FIG. 1C is a plot depicting example characteristic voltages of theselector device and the storage element of the memory cell of FIGS. 1Aand 1B, in accordance with various embodiments.

FIG. 2 is a cross-sectional view of an example selector device, inaccordance with various embodiments.

FIG. 3 is a schematic illustration of a memory device including selectordevices, in accordance with various embodiments.

FIG. 4 is a flow diagram of an illustrative method of manufacturing aselector device, in accordance with various embodiments.

FIG. 5 depicts top views of a wafer and dies that may include any of theselector devices or memory cells disclosed herein.

FIG. 6 is a cross-sectional side view of an integrated circuit (IC)device that may include any of the selector devices or memory cellsdisclosed herein.

FIG. 7 is a cross-sectional side view of a device assembly that mayinclude any of the selector devices or memory cells disclosed herein.

FIG. 8 is a block diagram of an example computing device that mayinclude any of the selector devices or memory cells disclosed herein, inaccordance with various embodiments.

DETAILED DESCRIPTION

Disclosed herein are selector devices and related devices andtechniques. In some embodiments, a selector device may include a firstelectrode, a second electrode, and a selector material between the firstelectrode and the second electrode. The selector material may includegermanium, tellurium, and sulfur, as discussed further herein.

Some memory devices may be considered “standalone” devices in that theyare included in a chip that does not also include computing logic (e.g.,transistors for performing processing operations). Other memory devicesmay be included in a chip along with computing logic and may be referredto as “embedded” memory devices. Using embedded memory to supportcomputing logic may improve performance by bringing the memory and thecomputing logic closer together and eliminating interfaces that increaselatency. However, because embedded memory devices may have to meet thethermal, electrical, manufacturing, and other constraints imposed by thecomputing logic, some conventional memory architectures used instandalone devices may not be suitable for high performance embeddedapplications. For example, some conventional standalone memory devicesmay have a lower range of temperatures at which they should bemaintained to avoid material degradation relative to the fabricationtemperatures used during the manufacture of conventional computinglogic; this “low temperature budget” for the memory devices may precludethe integration of these memory devices with computing logic whosefabrication uses higher temperatures. In another example, someconventional standalone memory devices may require high voltages forproper operation (e.g., for switching between different memory states);these voltages may be higher than those that can be effectively providedby conventional computing logic.

Various ones of the selector devices, memory cells, and/or memory arraysdisclosed herein may enable the use of high density embedded memory incomputing chips (e.g., embedded non-volatile memory, “eNVM”). Forexample, various ones of the selector devices, memory cells, and/ormemory arrays disclosed herein may include a selector material that willnot significantly degrade (e.g., by crystallization) at the operatingtemperatures of computing logic and thus may be used in embeddedapplications. More generally, various ones of the selector devices,memory cells, and/or memory arrays disclosed herein may provideperformance improvements over some conventional devices.

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, embodiments that may be practiced. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent disclosure. Therefore, the following detailed description is notto be taken in a limiting sense.

Various operations may be described as multiple discrete actions oroperations in turn in a manner that is most helpful in understanding theclaimed subject matter. However, the order of description should not beconstrued as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order from the described embodiment. Various additionaloperations may be performed, and/or described operations may be omittedin additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B, and C). The term “between,” when usedwith reference to measurement ranges, is inclusive of the ends of themeasurement ranges. As used herein, the notation “A/B/C” means (A), (B),and/or (C). As used herein, a “dopant” refers to an impurity materialthat is included in another material to alter the electrical propertiesof the other material. As used herein, an “embedded memory” refers to amemory device or array of devices that is included in a die along withcomputing logic (e.g., transistors arranged to perform processingoperations).

The description uses the phrases “in an embodiment” or “in embodiments,”which may each refer to one or more of the same or differentembodiments. Furthermore, the terms “comprising,” “including,” “having,”and the like, as used with respect to embodiments of the presentdisclosure, are synonymous. The disclosure may use perspective-baseddescriptions such as “above,” “below,” “top,” “bottom,” and “side”; suchdescriptions are used to facilitate the discussion and are not intendedto restrict the application of disclosed embodiments. The disclosure mayuse the singular term “layer,” but the term “layer” should be understoodto refer to assemblies that may include multiple different materiallayers. The accompanying drawings are not necessarily drawn to scale.

FIG. 1A is a perspective view of a portion of a memory array 100including a selector device 130, in accordance with various embodiments.The memory array 100 may be a cross-point array including memory cells102 located at the intersections of conductive lines 104 and conductivelines 106. In some embodiments, the conductive lines 104 may be wordlines and the conductive lines 106 may be bit lines, for example; forease of discussion, this terminology may be used herein to refer to theconductive lines 104 and the conductive lines 106. In the embodimentillustrated in FIG. 1A, the word lines 104 may be parallel to each otherand may be arranged perpendicularly to the bit lines 106 (whichthemselves may be parallel to each other), but any other suitablearrangement may be used. The word lines 104 and/or the bit lines 106 maybe formed of any suitable conductive material, such as a metal (e.g.,tungsten, copper, titanium, or aluminum). In some embodiments, thememory array 100 depicted in FIG. 1A may be a portion (e.g., a deck 101)of a three-dimensional array in which other arrangements of memory cells102 like the arrangement in the memory array 100 of FIG. 1A are locatedat different levels (e.g., above or below the depicted memory array100). The memory arrays 100 disclosed herein may include one or moredecks 101 (e.g., two, three, or four decks 101).

Each memory cell 102 may include a storage element 120 coupled in serieswith an associated selector device 130. Generally, a storage element 120may be programmed to a target data state (e.g., corresponding to aparticular resistance state) by applying an electric field or energy(e.g., positive or negative voltage or current pulses) to the storageelement 120 for a particular duration. In some embodiments, a storageelement 120 may include a memory material 110 disposed between a pair ofelectrodes 108 and 112. In some embodiments, the storage element 120 maybe a non-volatile storage element. The storage element 120 may be, forexample, a resistive storage element (also referred to herein as a“resistive switch”) that, during operation, switches between twodifferent non-volatile states: a high resistance state (HRS) and a lowresistance state (LRS). The state of a resistive storage element may beused to represent a data bit (e.g., a “1” for HRS and a “0” for LRS, orvice versa). A resistive storage element may have a voltage thresholdbeyond which the resistive storage element is in the LRS; driving aresistive storage element into the LRS may be referred to as SET (withan associated SET threshold voltage). Similarly, a resistive storageelement may have a voltage threshold beyond which the resistive storageelement is in the HRS; driving a resistive storage element into the HRSmay be referred to as RESET (with an associated RESET thresholdvoltage).

The storage element 120 may be, for example, a resistive random accessmemory (RRAM) device; in such embodiments, the memory material 110 mayinclude an oxygen exchange layer (e.g., hafnium) and an oxide layer, asknown in the art. The storage element 120 may be, for example, a metalfilament memory device (e.g., a conductive bridging random access memory(CBRAM) device); in such embodiments, the memory material 110 mayinclude a solid electrolyte, one of the electrodes 108 and 112 may be anelectrochemically active material (e.g., silver or copper), and theother of the electrodes 108 and 112 may be an inert material (e.g., aninert metal), as known in the art. A chemical barrier layer (e.g.,tantalum, tantalum nitride, or tungsten) may be disposed between theelectrochemically active electrode and the solid electrolyte to mitigatediffusion of the electrochemically active material into the solidelectrolyte, in some such embodiments. In some embodiments, the storageelement 120 may be a phase change memory (PCM) device; in suchembodiments, the memory material 110 may include a chalcogenide or otherphase change memory material. In some embodiments, the storage element120 may be a magnetoresistive random access memory (M RAM) device; insuch embodiments, the electrodes 108 and 112 may be magnetic (e.g.,ferromagnetic), and the memory material 110 may be a thin insulatingtunnel barrier material. As known in the art, MRAM devices may operateon the principle of tunnel magnetoresistance between two magnetic layers(the electrodes 108 and 112) separated by a tunnel junction (the memorymaterial 110). An MRAM device may have two stable states: when themagnetic moments of the two magnetic layers are aligned parallel to eachother, an MRAM device may be in the LRS, and when aligned antiparallel,an MRAM device may be in the HRS. In some embodiments, the storageelement 120 may be a spin-transfer torque magnetic random access memory(STT-M RAM) device; in such embodiments, the electrodes 108 and 112 maybe magnetic (e.g., ferromagnetic), and the memory material 110 may be athin metallic tunnel barrier material. Like an MRAM device, an STT-MRAMdevice may have two stable states: when the magnetic moments of theelectrodes 108 and 112 are aligned parallel to each other, an STT-M RAMdevice may be in the LRS, and when aligned antiparallel, an STT-MRAMdevice may be in the HRS.

The selector device 130 may be a two-terminal device that may act as abipolar switch, controlling the flow of current through the storageelement 120. In some embodiments, the selector device 130 may include aselector material 114 disposed between a pair of electrodes 112 and 116.Note that, in the embodiment illustrated in FIG. 1A, the electrode 112of the selector device 130 is “shared” with the storage element 120 inthat the electrode 112 acts as an electrode for the selector device 130and for the storage element 120. In other embodiments of the memory cell102, the selector device 130 may not share any electrodes with thestorage element 120. During manufacture of the memory cell 102, theselector device 130 may be fabricated before or after the storageelement 120 is fabricated. Various embodiments of the selector device130 are discussed in detail below.

As illustrated in the schematic view in FIG. 1B of the memory cell 102,when the selector device 130 is in a conductive (i.e., low resistance)state, the “switch” may be closed; when the selector device 130 is in anon-conductive (i.e., high resistance) state, the “switch” may be open.The state of the selector device 130 may change in response to thevoltage applied across the selector device 130. FIG. 1C illustratesexample electrical characteristics of an example selector device 130 andan example storage element 120 when positive voltages are applied. TheI-V characteristic 140 represents behavior of an example selector device130, and the I-V characteristic 142 represents behavior of an examplestorage element 120.

As illustrated in FIG. 1C, the selector device 130 may be in a highresistance state (an “off state”) when the voltage across the selectordevice 130 increases from zero to the threshold voltage Von. When thevoltage across the selector device 130 reaches and exceeds the thresholdvoltage Von (and an associated on stage current Ion), the selectordevice 130 may enter a low resistance state (an “on state”) and mayconduct current of a positive polarity. When the voltage across theselector device 130 is decreased from the threshold voltage Von, theselector device 130 may remain in the on stage until a holding voltageVhold (and an associated holding current Ihold) is reached. When thevoltage across the selector device decreases to and beyond the holdingvoltage Vhold, the selector device 130 may enter the off state again. Insome embodiments, the selector devices 130 disclosed herein may have athreshold voltage Von between 0.4 volts and 2.5 volts, or 1 volt orless. A threshold voltage Von that is less than 2 volts, or less than 1volt, may be particularly suitable for some embedded memoryapplications. In some embodiments, the selector devices 130 disclosedherein may have an on stage current Ion that is greater than or equal to0.5 megaamperes per square centimeter. In some embodiments, the selectordevices 130 disclosed herein may have a holding voltage Vhold between0.1 volts and 2.5 volts (e.g., between 0.1 volts and 1 volt for embeddedmemory applications, and between 0.5 volts and 2 volts for standalonememory applications).

Note that the holding voltage Vhold may be less than the thresholdvoltage Von, as illustrated in FIG. 1C. In some embodiments, it may bedesirable for the holding voltage Vhold to be approximately the same as,or close to, the threshold voltage Von. In other embodiments, it may bedesirable for the holding voltage Vhold to be less than the thresholdvoltage Von. For example, when the holding voltage Vhold is less thanthe threshold voltage Von, the voltage across an “on” selector device130 may be decreased from the threshold voltage Von and the selectordevice 130 may remain in the on state; this may reduce the powerrequired to keep the selector device 130 on (e.g., during a readoperation of the associated storage element 120) and thus may improvepower efficiency.

Some selector devices 130 may require or benefit from the application ofan initial formation voltage Vform that is larger than the thresholdvoltage Von when the selector device is first used;

FIG. 1C includes a curve 141 illustrating an example initial formationphase. This initial formation phase (sometimes referred to as “firstfire”) may “break down” the selector material 114 (e.g., by introducingsome of the material of the electrodes 112 and 116 into the selectormaterial 114 or creating regions of inhomogeneous material compositionin the selector material 114) so as to allow subsequent on/off behavioras described above. As noted above, FIG. 1C also depicts an example I-Vcharacteristic 142 for a storage element 120 (e.g., an RRAM device) witha SET threshold voltage Vset. The SET threshold voltage Vset may begreater than the threshold voltage Von for the selector device 130.

Disclosed herein are selector devices 130 having selector material 114whose composition may have a higher thermal budget relative to someconventional selector materials. As noted above, some of these selectordevices 130 may thus be used in embedded applications (e.g., byincluding the selector devices 130 in the backend of a die that alsoincludes computing logic, as discussed below).

The selector devices 130 disclosed herein and the associated memorycells 102 may take any of a number of forms. For example, FIG. 2 is across-sectional view of a selector device 130, in accordance withvarious embodiments. The selector device 130 of FIG. 2 may include anelectrode 116, an electrode 112, and a selector material 114 between theelectrodes 116 and 112.

The electrodes 112 and 116 may be composed of any suitable material. Insome embodiments, the electrodes 112 and 116 may be composed oftantalum, platinum, hafnium, cobalt, indium, iridium, copper, tungsten,ruthenium, palladium, and/or carbon. The electrodes 112 and 116 may becomposed of pure forms of these elements, combinations of theseelements, or combinations of these elements and other elements, in someembodiments. For example, in some embodiments, the electrode 112 and/orthe electrode 116 may include a conductive nitride (e.g., tantalumnitride or titanium nitride). In some embodiments, the materialcompositions of the electrodes 112 and 116 may be the same, while inother embodiments, the material compositions of the electrodes 112 and116 may be different.

In some embodiments of the selector devices 130 disclosed herein, thegeometries of the electrodes 112 and 116 may be the same or may differ.For example, the electrodes 112 and 116 may have the same or differentsurface areas. In some embodiments, the cross-sectional width 143 of theelectrode 112, the selector material 114, and/or the electrode 116 maybe between 5 nanometers and 50 nanometers.

The selector material 114 may be a thin film including germanium,tellurium, and sulfur. The selector material 114 may include less than50 atomic-percent of germanium. The selector material 114 may have anatomic ratio of sulfur to tellurium that is greater than 1. For example,the selector material 114 may include Ge_(x)Te_(y)S_(1-x-y), with x lessthan 0.5, and (1-x-y)/y greater than 1.

Such selector materials 114 may have a glass transition temperature thatis greater than 350 degrees Celsius (e.g., greater than 400 degreesCelsius) and thus may not crystallize at these temperatures.Consequently, these selector materials 114 may be included in selectordevices 130 formed during back end of line (BEOL) manufacturing of a diethat also includes computing logic, without undergoing significantdamage or undesirable modification. Some conventional selector materials(e.g., some conventional chalcogenides) may not have glass transition orcrystallization temperatures that enable them to be used in a BEOLprocess for computing logic.

In some embodiments, the selector material 114 may further include adopant. The amount and type of dopant may be selected to adjust thecrystallization temperature of the selector material 114 (e.g., toincrease the crystallization temperature of the selector material 114).In some embodiments, the dopant may include silicon or nitrogen. In someembodiments, the dopant may be present in the selector material at aconcentration between 2 atomic-percent and 15 atomic-percent. A dopantincluded in the selector material 114 may further increase thetemperature at which the selector material 114 crystallizes, increasingthe thermal budget of the selector material.

The thicknesses of the materials included in the selector device 130 ofFIG. 2 may take any suitable values. For example, in some embodiments,the electrode 112 may have a thickness 132 between 1 nanometer and 100nanometers, the selector material 114 may have a thickness 134 between 2nanometers and 80 nanometers, and the electrode 116 may have a thickness136 between 1 nanometer and 100 nanometers. When a selector device 130is used in conjunction with an STT-M RAM storage element 120 in a memorycell, for example, the thickness 136 of the electrode 116 may bedifferent from the thickness 132 of the electrode 112.

A memory array 100 including a selector device 130 may be controlled inany suitable manner. For example, FIG. 3 is a schematic illustration ofa memory device 200 including a memory array 100 having memory cells 102with storage elements 120 and selector devices 130, in accordance withvarious embodiments. As discussed above, each memory cell 102 mayinclude a storage element 120 connected in series with any of theembodiments of the selector devices 130 disclosed herein. The memorydevice 200 of FIG. 3 may be a bidirectional cross-point array in whicheach column is associated with a bit line 106 driven by column selectcircuitry 210. Each row may be associated with a word line 104 driven byrow select circuitry 206. During operation, read/write control circuitry208 may receive memory access requests (e.g., from one or moreprocessing devices or communication chips of a computing device, such asthe computing device 2000 discussed below) and may respond by generatingan appropriate control signal (e.g., read, write 0, or write 1), asknown in the art. The read/write control circuitry 208 may control therow select circuitry 206 and the column select circuitry 210 to selectthe desired memory cell(s) 102. Voltage supplies 204 and 212 may becontrolled to provide the voltage(s) necessary to bias the memory array100 to facilitate the requested action on one or more memory cells 102.Row select circuitry 206 and column select circuitry 210 may applyappropriate voltages across the memory array 100 to access the selectedmemory cells 102 (e.g., by providing appropriate voltages to the memorycells 102 to allow the desired selector devices 130 to conduct). Rowselect circuitry 206, column select circuitry 210, and read/writecontrol circuitry 208 may be implemented using any devices andtechniques known in the art.

Any suitable techniques may be used to manufacture the selector devices130 and memory cells 102 disclosed herein. FIG. 4 is a flow diagram ofan illustrative method 1000 of manufacturing a selector device, inaccordance with various embodiments. Although the operations discussedbelow with reference to the method 1000 are illustrated in a particularorder and depicted once each, these operations may be repeated orperformed in a different order (e.g., in parallel), as suitable.Additionally, various operations may be omitted, as suitable. Variousoperations of the method 1000 may be illustrated with reference to oneor more of the embodiments discussed above, but the method 1000 may beused to manufacture any suitable selector device (including any suitableones of the embodiments disclosed herein).

At 1002, a first electrode may be formed (e.g., by physical vapordeposition (PVD), such as sputtering). For example, the electrode 112may be formed on the memory material 110 of a storage element 120. Thefirst electrode may take any of the forms disclosed herein.

At 1004, a selector material may be formed on the first electrode. Theselector material may include germanium, tellurium, and sulfur. Forexample, the selector material 114 may be formed on the electrode 112using PVD (e.g., radio frequency or pulsed DC sputtering) or atomiclayer deposition (ALD). The selector material may take any of the formsdisclosed herein (e.g., Ge_(x)Te_(y)S_(1-x-y), with x less than 0.5, and(1-x-y)/y greater than 1).

At 1006, a second electrode may be formed on the selector material. Forexample, the electrode 116 may be formed on the selector material 114.The second electrode may take any of the forms disclosed herein.

The selector devices 130 and memory cells 102 disclosed herein may beincluded in any suitable electronic device. FIG. 5 depicts top views ofa wafer 450 and dies 452 that may be formed from the wafer 450; the dies452 may include any of the selector devices 130 or memory cells 102disclosed herein. The wafer 450 may include semiconductor material andmay include one or more dies 452 having integrated circuit (IC) elements(e.g., selector devices 130 and storage elements 120) formed on asurface of the wafer 450. Each of the dies 452 may be a repeating unitof a semiconductor product that includes any suitable device (e.g., thememory device 200). After the fabrication of the semiconductor productis complete, the wafer 450 may undergo a singulation process in whichthe dies 452 are separated from one another to provide discrete “chips”of the semiconductor product. A die 452 may include one or more selectordevices 130 or memory cells 102 and/or supporting circuitry to routeelectrical signals to the selector devices 130 or memory cells 102(e.g., interconnects including conductive lines 104 and 106), as well asany other IC components. In some embodiments, the wafer 450 or the die452 may include other memory devices, logic devices (e.g., AND, OR,NAND, or NOR gates), or any other suitable circuit element. Multipleones of these devices may be combined on a single die 452. For example,a memory device formed by multiple memory arrays (e.g., multiple memoryarrays 100) may be formed on a same die 452 as a processing device(e.g., the processing device 2002 of FIG. 8) or other logic that isconfigured to store information in the memory devices or executeinstructions stored in the memory array.

FIG. 6 is a cross-sectional side view of an IC device 1600 that mayinclude any of the selector devices 130 or memory cells 102 disclosedherein. The IC device 1600 may be formed on a substrate 1602 (e.g., thewafer 450 of FIG. 5) and may be included in a die (e.g., the die 452 ofFIG. 5). The substrate 1602 may be a semiconductor substrate composed ofsemiconductor material systems including, for example, n-type or p-typematerials systems (or a combination of both). The substrate 1602 mayinclude, for example, a crystalline substrate formed using a bulksilicon or a silicon-on-insulator (SOI) substructure. In someembodiments, the substrate 1602 may be formed using alternativematerials, which may or may not be combined with silicon, that includebut are not limited to germanium, indium antimonide, lead telluride,indium arsenide, indium phosphide, gallium arsenide, or galliumantimonide. Further materials classified as group II-VI, III-V, or IVmay also be used to form the substrate 1602. Although a few examples ofmaterials from which the substrate 1602 may be formed are describedhere, any material that may serve as a foundation for an IC device 1600may be used. The substrate 1602 may be part of a singulated die (e.g.,the dies 452 of FIG. 5) or a wafer (e.g., the wafer 450 of FIG. 5).

The IC device 1600 may include one or more device layers 1604 disposedon the substrate 1602. The device layer 1604 may include features of oneor more transistors 1640 (e.g., metal oxide semiconductor field-effecttransistors (MOSFETs)) formed on the substrate 1602. The device layer1604 may include, for example, one or more source and/or drain (S/D)regions 1620, a gate 1622 to control current flow in the transistors1640 between the S/D regions 1620, and one or more S/D contacts 1624 toroute electrical signals to/from the S/D regions 1620. The transistors1640 may include additional features not depicted for the sake ofclarity, such as device isolation regions, gate contacts, and the like.The transistors 1640 are not limited to the type and configurationdepicted in FIG. 5 and may include a wide variety of other types andconfigurations such as, for example, planar transistors, non-planartransistors, or a combination of both. Non-planar transistors mayinclude FinFET transistors, such as double-gate transistors or tri-gatetransistors, and wrap-around or all-around gate transistors, such asnanoribbon and nanowire transistors.

Each transistor 1640 may include a gate 1622 formed of at least twolayers, a gate dielectric and a gate electrode. The gate dielectric mayinclude one layer or a stack of layers. The one or more layers mayinclude silicon oxide, silicon dioxide, silicon carbide, and/or a high-kdielectric material. The high-k dielectric material may include elementssuch as hafnium, silicon, oxygen, titanium, tantalum, lanthanum,aluminum, zirconium, barium, strontium, yttrium, lead, scandium,niobium, and zinc. Examples of high-k materials that may be used in thegate dielectric include, but are not limited to, hafnium oxide, hafniumsilicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconiumoxide, zirconium silicon oxide, tantalum oxide, titanium oxide, bariumstrontium titanium oxide, barium titanium oxide, strontium titaniumoxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, andlead zinc niobate. In some embodiments, an annealing process may becarried out on the gate dielectric to improve its quality when a high-kmaterial is used.

The gate electrode may be formed on the gate dielectric and may includeat least one p-type work function metal or n-type work function metal,depending on whether the transistor 1640 is to be a p-type metal oxidesemiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS)transistor. In some implementations, the gate electrode may consist of astack of two or more metal layers, where one or more metal layers arework function metal layers and at least one metal layer is a fill metallayer. Further metal layers may be included for other purposes, such asa barrier layer. For a PMOS transistor, metals that may be used for thegate electrode include, but are not limited to, ruthenium, palladium,platinum, cobalt, nickel, and conductive metal oxides (e.g., rutheniumoxide), and any of the metals discussed below with reference to an NMOStransistor (e.g., for work function tuning). For an NMOS transistor,metals that may be used for the gate electrode include, but are notlimited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys ofthese metals, and carbides of these metals (e.g., hafnium carbide,zirconium carbide, titanium carbide, tantalum carbide, and aluminumcarbide), and any of the metals discussed above with reference to a PMOStransistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor1640 along the source-channel-drain direction, the gate electrode mayconsist of a U-shaped structure that includes a bottom portionsubstantially parallel to the surface of the substrate and two sidewallportions that are substantially perpendicular to the top surface of thesubstrate. In other embodiments, at least one of the metal layers thatform the gate electrode may simply be a planar layer that issubstantially parallel to the top surface of the substrate and does notinclude sidewall portions substantially perpendicular to the top surfaceof the substrate. In other embodiments, the gate electrode may consistof a combination of U-shaped structures and planar, non-U-shapedstructures. For example, the gate electrode may consist of one or moreU-shaped metal layers formed atop one or more planar, non-U-shapedlayers.

In some embodiments, a pair of sidewall spacers may be formed onopposing sides of the gate stack to bracket the gate stack. The sidewallspacers may be formed from materials such as silicon nitride, siliconoxide, silicon carbide, silicon nitride doped with carbon, and siliconoxynitride. Processes for forming sidewall spacers are well known in theart and generally include deposition and etching process steps. In someembodiments, a plurality of spacer pairs may be used; for instance, twopairs, three pairs, or four pairs of sidewall spacers may be formed onopposing sides of the gate stack.

The S/D regions 1620 may be formed within the substrate 1602 adjacent tothe gate 1622 of each transistor 1640. The S/D regions 1620 may beformed using an implantation/diffusion process or an etching/depositionprocess, for example. In the former process, dopants such as boron,aluminum, antimony, phosphorous, or arsenic may be ion-implanted intothe substrate 1602 to form the S/D regions 1620. An annealing processthat activates the dopants and causes them to diffuse farther into thesubstrate 1602 may follow the ion-implantation process. In the latterprocess, the substrate 1602 may first be etched to form recesses at thelocations of the S/D regions 1620. An epitaxial deposition process maythen be carried out to fill the recesses with material that is used tofabricate the S/D regions 1620. In some implementations, the S/D regions1620 may be fabricated using a silicon alloy such as silicon germaniumor silicon carbide. In some embodiments, the epitaxially depositedsilicon alloy may be doped in situ with dopants such as boron, arsenic,or phosphorous. In some embodiments, the S/D regions 1620 may be formedusing one or more alternate semiconductor materials such as germanium ora group III-V material or alloy. In further embodiments, one or morelayers of metal and/or metal alloys may be used to form the S/D regions1620.

Electrical signals, such as power and/or input/output (I/O) signals, maybe routed to and/or from the devices (e.g., transistors 1640) of thedevice layer 1604 through one or more interconnect layers disposed onthe device layer 1604 (illustrated in FIG. 6 as interconnect layers1606-1610). For example, electrically conductive features of the devicelayer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may beelectrically coupled with the interconnect structures 1628 of theinterconnect layers 1606-1610. The one or more interconnect layers1606-1610 may form a metallization stack (also referred to as an “ILDstack”) 1619 of the IC device 1600.

In some embodiments, one or more selector devices 130, memory cells 102,and/or memory arrays 100 may be disposed in one or more of theinterconnect layers 1606-1610, in accordance with any of the techniquesdisclosed herein. FIG. 5 illustrates a single memory array 100 in theinterconnect layer 1608 for illustration purposes, but any number andstructure of memory arrays 100, memory cells 102, and/or selectordevices 130 may be included in any one or more of the layers in ametallization stack 1619 (e.g., memory arrays 100 with one or more decks101 of memory cells 102). A memory array 100 included in themetallization stack 1619, in combination with computing logic (e.g.,some or all of the transistors 1640) in the IC device 1600, may bereferred to as an “embedded” memory array, as discussed above. Inembodiments in which the IC device 1600 does not include any computinglogic but does include one or more memory arrays 100, the IC device 1600may be referred to as a “standalone” memory device. One or more selectordevices 130, memory cells 102, and/or memory arrays 100 in themetallization stack 1619 may be coupled to any suitable ones of thedevices in the device layer 1604, and/or to one or more of theconductive contacts 1636 (discussed below).

The interconnect structures 1628 may be arranged within the interconnectlayers 1606-1610 to route electrical signals according to a wide varietyof designs (in particular, the arrangement is not limited to theparticular configuration of interconnect structures 1628 depicted inFIG. 5). Although a particular number of interconnect layers 1606-1610is depicted in FIG. 5, embodiments of the present disclosure include ICdevices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 1628 may include lines1628 a and/or vias 1628 b filled with an electrically conductivematerial such as a metal. The lines 1628 a may be arranged to routeelectrical signals in a direction of a plane that is substantiallyparallel with a surface of the substrate 1602 upon which the devicelayer 1604 is formed. For example, the lines 1628 a may route electricalsignals in a direction in and out of the page from the perspective ofFIG. 5. The vias 1628 b may be arranged to route electrical signals in adirection of a plane that is substantially perpendicular to the surfaceof the substrate 1602 upon which the device layer 1604 is formed. Insome embodiments, the vias 1628 b may electrically couple lines 1628 aof different interconnect layers 1606-1610 together.

The interconnect layers 1606-1610 may include a dielectric material 1626disposed between the interconnect structures 1628, as shown in FIG. 5.In some embodiments, the dielectric material 1626 disposed between theinterconnect structures 1628 in different ones of the interconnectlayers 1606-1610 may have different compositions; in other embodiments,the composition of the dielectric material 1626 between differentinterconnect layers 1606-1610 may be the same.

A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may beformed directly on the device layer 1604. In some embodiments, the firstinterconnect layer 1606 may include lines 1628 a and/or vias 1628 b, asshown. The lines 1628 a of the first interconnect layer 1606 may becoupled with contacts (e.g., the S/D contacts 1624) of the device layer1604.

A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may beformed directly on the first interconnect layer 1606. In someembodiments, the second interconnect layer 1608 may include vias 1628 bto couple the lines 1628 a of the second interconnect layer 1608 withthe lines 1628 a of the first interconnect layer 1606. Although thelines 1628 a and the vias 1628 b are structurally delineated with a linewithin each interconnect layer (e.g., within the second interconnectlayer 1608) for the sake of clarity, the lines 1628 a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneouslyfilled during a dual-damascene process) in some embodiments.

A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (andadditional interconnect layers, as desired) may be formed in successionon the second interconnect layer 1608 according to similar techniquesand configurations described in connection with the second interconnectlayer 1608 or the first interconnect layer 1606. In some embodiments,the interconnect layers that are “higher up” in the metallization stack1619 in the IC device 1600 (i.e., further away from the device layer1604) may be thicker.

The IC device 1600 may include a solder resist material 1634 (e.g.,polyimide or similar material) and one or more conductive contacts 1636formed on the interconnect layers 1606-1610. In FIG. 5, the conductivecontacts 1636 are illustrated as taking the form of bond pads. Theconductive contacts 1636 may be electrically coupled with theinterconnect structures 1628 and configured to route the electricalsignals of the transistor(s) 1640 to other external devices. Forexample, solder bonds may be formed on the one or more conductivecontacts 1636 to mechanically and/or electrically couple a chipincluding the IC device 1600 with another component (e.g., a circuitboard). The IC device 1600 may include additional or alternatestructures to route the electrical signals from the interconnect layers1606-1610; for example, the conductive contacts 1636 may include otheranalogous features (e.g., posts) that route the electrical signals toexternal components.

FIG. 7 is a cross-sectional side view of a device assembly 400 that mayinclude any of the selector devices 130 or memory cells 102 disclosedherein in one or more packages. A “package” may refer to an electroniccomponent that includes one or more IC devices (e.g., the IC devices1600 discussed above with reference to FIG. 6) that are structured forcoupling to other components; for example, a package may include a diecoupled to a package substrate that provides electrical routing andmechanical stability to the die. The device assembly 400 includes anumber of components disposed on a circuit board 402. The deviceassembly 400 may include components disposed on a first face 440 of thecircuit board 402 and an opposing second face 442 of the circuit board402; generally, components may be disposed on one or both faces 440 and442.

In some embodiments, the circuit board 402 may be a printed circuitboard (PCB) including multiple metal layers separated from one anotherby layers of dielectric material and interconnected by electricallyconductive vias. Any one or more of the metal layers may be formed in adesired circuit pattern to route electrical signals (optionally inconjunction with other metal layers) between the components coupled tothe circuit board 402. In other embodiments, the circuit board 402 maybe a package substrate or flexible board.

The device assembly 400 illustrated in FIG. 7 includes apackage-on-interposer structure 436 coupled to the first face 440 of thecircuit board 402 by coupling components 416. The coupling components416 may electrically and mechanically couple the package-on-interposerstructure 436 to the circuit board 402 and may include solder balls,male and female portions of a socket, an adhesive, an underfillmaterial, and/or any other suitable electrical and/or mechanicalcoupling structure.

The package-on-interposer structure 436 may include a package 420coupled to an interposer 404 by coupling components 418. The couplingcomponents 418 may take any suitable form for the application, such asthe forms discussed above with reference to the coupling components 416.Although a single package 420 is shown in FIG. 7, multiple packages maybe coupled to the interposer 404; indeed, additional interposers may becoupled to the interposer 404. The interposer 404 may provide anintervening substrate used to bridge the circuit board 402 and thepackage 420. The package 420 may include one or more selector devices130 or memory cells 102, for example. Generally, the interposer 404 mayspread a connection to a wider pitch or reroute a connection to adifferent connection. For example, the interposer 404 may couple thepackage 420 (e.g., a die) to a ball grid array (BGA) of the couplingcomponents 416 for coupling to the circuit board 402. In the embodimentillustrated in FIG. 7, the package 420 and the circuit board 402 areattached to opposing sides of the interposer 404; in other embodiments,the package 420 and the circuit board 402 may be attached to a same sideof the interposer 404. In some embodiments, three or more components maybe interconnected by way of the interposer 404.

The interposer 404 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In some embodiments, the interposer 404 maybe formed of alternate rigid or flexible materials that may include thesame materials described above for use in a semiconductor substrate,such as silicon, germanium, and other group III-V and group IVmaterials. The interposer 404 may include metal interconnects 408 andvias 410, including but not limited to through-silicon vias (TSVs) 406.The interposer 404 may further include embedded devices 414, includingboth passive and active devices. Such devices may include, but are notlimited to, capacitors, decoupling capacitors, resistors, inductors,fuses, diodes, transformers, sensors, electrostatic discharge (ESD)devices, and memory devices (e.g., the selector devices 130 or memorycells 102). More complex devices such as radio frequency (RF) devices,power amplifiers, power management devices, antennas, arrays, sensors,and microelectromechanical systems (MEMS) devices may also be formed onthe interposer 404. The package-on-interposer structure 436 may take theform of any of the package-on-interposer structures known in the art.

The device assembly 400 may include a package 424 coupled to the firstface 440 of the circuit board 402 by coupling components 422. Thecoupling components 422 may take the form of any of the embodimentsdiscussed above with reference to the coupling components 416, and thepackage 424 may take the form of any of the embodiments discussed abovewith reference to the package 420. The package 424 may include one ormore selector devices 130 or memory cells 102, for example.

The device assembly 400 illustrated in FIG. 7 includes apackage-on-package structure 434 coupled to the second face 442 of thecircuit board 402 by coupling components 428. The package-on-packagestructure 434 may include a package 426 and a package 432 coupledtogether by coupling components 430 such that the package 426 isdisposed between the circuit board 402 and the package 432. The couplingcomponents 428 and 430 may take the form of any of the embodiments ofthe coupling components 416 discussed above, and the packages 426 and432 may take the form of any of the embodiments of the package 420discussed above. Each of the packages 426 and 432 may include one ormore selector devices 130 or memory cells 102, for example.

FIG. 8 is a block diagram of an example computing device 2000 that mayinclude any of the selector devices 130 or memory cells 102 disclosedherein. A number of components are illustrated in FIG. 8 as included inthe computing device 2000, but any one or more of these components maybe omitted or duplicated, as suitable for the application. In someembodiments, some or all of the components included in the computingdevice 2000 may be attached to one or more PCBs (e.g., a motherboard).In some embodiments, various ones of these components may be fabricatedonto a single system-on-a-chip (SoC) die. Additionally, in variousembodiments, the computing device 2000 may not include one or more ofthe components illustrated in FIG. 8, but the computing device 2000 mayinclude interface circuitry for coupling to the one or more components.For example, the computing device 2000 may not include a display device2006 but may include display device interface circuitry (e.g., aconnector and driver circuitry) to which a display device 2006 may becoupled. In another set of examples, the computing device 2000 may notinclude an audio input device 2024 or an audio output device 2008 butmay include audio input or output device interface circuitry (e.g.,connectors and supporting circuitry) to which an audio input device 2024or audio output device 2008 may be coupled.

The computing device 2000 may include a processing device 2002 (e.g.,one or more processing devices). As used herein, the term “processingdevice” or “processor” may refer to any device or portion of a devicethat processes electronic data from registers and/or memory to transformthat electronic data into other electronic data that may be stored inregisters and/or memory. The processing device 2002 may interface withone or more of the other components of the computing device 2000 (e.g.,the communication chip 2012 discussed below, the display device 2006discussed below, etc.) in a conventional manner. The processing device2002 may include one or more digital signal processors (DSPs),application-specific integrated circuits (ASICs), central processingunits (CPUs), graphics processing units (GPUs), cryptoprocessors(specialized processors that execute cryptographic algorithms withinhardware), server processors, or any other suitable processing devices.In some embodiments, the processing device 2002 may include computinglogic that is part of a die that includes embedded memory, such as anyof the memory cells 102 and/or memory arrays 100 disclosed herein.

The computing device 2000 may include a memory 2004, which may itselfinclude one or more memory devices such as volatile memory (e.g.,dynamic random access memory (DRAM)), non-volatile memory (e.g.,read-only memory (ROM)), flash memory, solid state memory, and/or a harddrive. The memory 2004 may include one or more selector devices 130 ormemory cells 102 or memory arrays 100 or memory devices 200, asdisclosed herein. In some embodiments, the memory 2004 may includememory that shares a die with the processing device 2002. This memorymay be used as cache memory and may include embedded dynamic randomaccess memory (eDRAM) or STT-M RAM.

In some embodiments, the computing device 2000 may include acommunication chip 2012 (e.g., one or more communication chips). Forexample, the communication chip 2012 may be configured for managingwireless communications for the transfer of data to and from thecomputing device 2000. The term “wireless” and its derivatives may beused to describe circuits, devices, systems, methods, techniques,communications channels, etc., that may communicate data through the useof modulated electromagnetic radiation through a nonsolid medium. Theterm does not imply that the associated devices do not contain anywires, although in some embodiments they might not.

The communication chip 2012 may implement any of a number of wirelessstandards or protocols, including but not limited to Institute forElectrical and Electronic Engineers (IEEE) standards including Wi-Fi(IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005Amendment), Long-Term Evolution (LTE) project along with any amendments,updates, and/or revisions (e.g., advanced LTE project, ultramobilebroadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE802.16 compatible Broadband Wireless Access (BWA) networks are generallyreferred to as WiMAX networks, an acronym that stands for WorldwideInteroperability for Microwave Access, which is a certification mark forproducts that pass conformity and interoperability tests for the IEEE802.16 standards. The communication chip 2012 may operate in accordancewith a Global System for Mobile Communication (GSM), General PacketRadio Service (GPRS), Universal Mobile Telecommunications System (UMTS),High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communication chip 2012 may operate in accordance with Enhanced Datafor GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN),Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN(E-UTRAN). The communication chip 2012 may operate in accordance withCode Division Multiple Access (CDMA), Time Division Multiple Access(TDMA), Digital Enhanced Cordless Telecommunications (DECT),Evolution-Data Optimized (EV-DO), and derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The communication chip 2012 may operate in accordance with otherwireless protocols in other embodiments. The computing device 2000 mayinclude an antenna 2022 to facilitate wireless communications and/or toreceive other wireless communications (such as AM or FM radiotransmissions).

In some embodiments, the communication chip 2012 may manage wiredcommunications, such as electrical, optical, or any other suitablecommunication protocols (e.g., the Ethernet). As noted above, thecommunication chip 2012 may include multiple communication chips. Forinstance, a first communication chip 2012 may be dedicated toshorter-range wireless communications such as Wi-Fi or Bluetooth, and asecond communication chip 2012 may be dedicated to longer-range wirelesscommunications such as global positioning system (GPS), EDGE, GPRS,CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a firstcommunication chip 2012 may be dedicated to wireless communications, anda second communication chip 2012 may be dedicated to wiredcommunications.

The computing device 2000 may include battery/power circuitry 2014. Thebattery/power circuitry 2014 may include one or more energy storagedevices (e.g., batteries or capacitors) and/or circuitry for couplingcomponents of the computing device 2000 to an energy source separatefrom the computing device 2000 (e.g., AC line power).

The computing device 2000 may include a display device 2006 (orcorresponding interface circuitry, as discussed above). The displaydevice 2006 may include any visual indicators, such as a heads-updisplay, a computer monitor, a projector, a touchscreen display, aliquid crystal display (LCD), a light-emitting diode display, or a flatpanel display.

The computing device 2000 may include an audio output device 2008 (orcorresponding interface circuitry, as discussed above). The audio outputdevice 2008 may include any device that generates an audible indicator,such as speakers, headsets, or earbuds.

The computing device 2000 may include an audio input device 2024 (orcorresponding interface circuitry, as discussed above). The audio inputdevice 2024 may include any device that generates a signalrepresentative of a sound, such as microphones, microphone arrays, ordigital instruments (e.g., instruments having a musical instrumentdigital interface (MIDI) output).

The computing device 2000 may include a GPS device 2018 (orcorresponding interface circuitry, as discussed above). The GPS device2018 may be in communication with a satellite-based system and mayreceive a location of the computing device 2000, as known in the art.

The computing device 2000 may include an other output device 2010 (orcorresponding interface circuitry, as discussed above). Examples of theother output device 2010 may include an audio codec, a video codec, aprinter, a wired or wireless transmitter for providing information toother devices, or an additional storage device.

The computing device 2000 may include an other input device 2020 (orcorresponding interface circuitry, as discussed above). Examples of theother input device 2020 may include an accelerometer, a gyroscope, acompass, an image capture device, a keyboard, a cursor control devicesuch as a mouse, a stylus, a touchpad, a bar code reader, a QuickResponse (QR) code reader, any sensor, or a radio frequencyidentification (RFID) reader.

The computing device 2000 or a subset of its components may have anyappropriate form factor, such as a hand-held or mobile computing device(e.g., a cell phone, a smart phone, a mobile internet device, a musicplayer, a tablet computer, a laptop computer, a netbook computer, anultrabook computer, a personal digital assistant (PDA), an ultramobilepersonal computer, etc.), a desktop computing device, a server or othernetworked computing component, a printer, a scanner, a monitor, aset-top box, an entertainment control unit, a vehicle control unit, adigital camera, a digital video recorder, or a wearable computingdevice.

The following paragraphs provide various examples of the embodimentsdisclosed herein.

Example 1 is a selector device, including: a first electrode; a secondelectrode; and a selector material between the first electrode and thesecond electrode, wherein the selector material includes germanium,tellurium, and sulfur, the selector material includes less than 50atomic-percent of germanium, and the selector material has an atomicratio of sulfur to tellurium that is greater than 1.

Example 2 may include the subject matter of Example 1, and may furtherspecify that the selector material further includes silicon.

Example 3 may include the subject matter of Example 2, and may furtherspecify that the selector material includes between 2 atomic-percent and15 atomic-percent of silicon.

Example 4 may include the subject matter of any of Examples 1-3, and mayfurther specify that the selector material further includes nitrogen.

Example 5 may include the subject matter of Example 4, and may furtherspecify that the selector material includes between 2 atomic-percent and15 atomic-percent of nitrogen.

Example 6 may include the subject matter of any of Examples 1-5, and mayfurther specify that the selector material includesGe_(x)Te_(y)S_(1-x-y).

Example 7 may include the subject matter of any of Examples 1-6, and mayfurther specify that the selector material has a thickness between 2nanometers and 80 nanometers.

Example 8 may include the subject matter of any of Examples 1-7, and mayfurther specify that the first electrode or the second electrodeincludes tantalum, platinum, hafnium, cobalt, indium, iridium, copper,or tungsten.

Example 9 may include the subject matter of any of Examples 1-8, and mayfurther specify that the selector device has a threshold voltage that isless than 1 volt.

Example 10 may include the subject matter of any of Examples 1-9, andmay further specify that the selector device has a holding voltagebetween 0.1 volts and 1 volt.

Example 11 may include the subject matter of any of Examples 1-10, andmay further specify that at least one of the first electrode and thesecond electrode is shared with a storage element.

Example 12 may include the subject matter of Example 11, and may furtherspecify that the storage element is a resistive random access memory(RRAM) device, a phase change memory (PCM) device, or a spin-transfertorque magnetic random access memory (STT-MRAM) device.

Example 13 is a memory array, including a memory cell, wherein thememory cell includes a storage element and a selector device coupled tothe storage element, wherein the selector device includes a selectormaterial, the selector material includes germanium, tellurium, andsulfur, the selector material includes less than 50 atomic-percent ofgermanium, and the selector material has an atomic ratio of sulfur totellurium that is greater than 1.

Example 14 may include the subject matter of Example 13, and may furtherspecify that the selector device includes a first electrode and a secondelectrode, the selector material is between the first electrode and thesecond electrode, and the first electrode or the second electrode isalso an electrode of the storage element.

Example 15 may include the subject matter of any of Examples 13-14, andmay further specify that the selector material further includes adopant.

Example 16 may include the subject matter of any of Examples 13-15, andmay further specify that the memory array includes a plurality of memorycells.

Example 17 may include the subject matter of Example 16, and may furtherspecify that the plurality of memory cells is arranged in multiple decksof memory cells.

Example 18 may include the subject matter of any of Examples 13-17, andmay further specify that the storage element is a resistive randomaccess memory (RRAM) device, a phase change memory (PCM) device, or aspin-transfer torque magnetic random access memory (STT-MRAM) device.

Example 19 may include the subject matter of any of Examples 13-18, andmay further specify that the memory cell includes a first terminalcoupled to a bit line, and the memory cell includes a second terminalcoupled to a word line.

Example 20 is a method of manufacturing a selector device, including:forming a first electrode; forming a selector material on the firstelectrode, wherein the selector material includes germanium, tellurium,and sulfur, the selector material includes less than 50 atomic-percentof germanium, and the selector material has an atomic ratio of sulfur totellurium that is greater than 1; and forming a second electrode on theselector material.

Example 21 may include the subject matter of Example 20, and may furtherspecify that forming the selector material includes physical vapordeposition of the selector material.

Example 22 may include the subject matter of any of Examples 20-21, andmay further specify that forming the selector material includessputtering the selector material.

Example 23 may include the subject matter of Example 20, and may furtherspecify that forming the selector material includes atomic layerdeposition of the selector material.

Example 24 may include the subject matter of any of Examples 20-23, andmay further specify that the selector material further includes a dopanthaving a concentration between 2 atomic-percent and 15 atomic-percent.

Example 25 may include the subject matter of any of Examples 20-24, andmay further include forming a storage element in series with theselector device.

Example 26 may include the subject matter of Example 25, and may furtherspecify that the first electrode is shared with the storage element.

Example 27 may include the subject matter of Example 25, and may furtherspecify that the second electrode is shared with the storage element.

Example 28 is a computing device, including: a circuit board; and a diecommunicatively coupled to the circuit board, wherein the die includes amemory array, the memory array includes a memory cell having a storageelement coupled in series with a selector device, the selector deviceincludes a selector material, and the selector material includesgermanium, tellurium, and sulfur.

Example 29 may include the subject matter of Example 28, and may furtherspecify that the selector material includes less than 50 atomic-percentof germanium.

Example 30 may include the subject matter of any of Examples 28-29, andmay further specify that the selector material has an atomic ratio ofsulfur to tellurium that is greater than 1.

Example 31 may include the subject matter of any of Examples 28-30, andmay further specify that the die further includes computing logic.

Example 32 may include the subject matter of any of Examples 28-31, andmay further include a wireless communications device coupled to thecircuit board.

Example 33 may include the subject matter of any of Examples 28-32, andmay further specify that the storage element includes a resistive randomaccess memory (RRAM) device, a phase change memory (PCM) device, or aspin-transfer torque magnetic random access memory (STT-MRAM) device.

1. A selector device, comprising: a first electrode; a second electrode;and a selector material between the first electrode and the secondelectrode, the selector material having a glass transition temperaturethat is greater than 350 degrees Celsius.
 2. The selector device ofclaim 1, wherein the selector material further includes silicon.
 3. Theselector device of claim 2, wherein the selector material includesbetween 2 atomic-percent and 15 atomic-percent of silicon.
 4. Theselector device of claim 1, wherein the selector material furtherincludes nitrogen.
 5. The selector device of claim 4, wherein theselector material includes between 2 atomic-percent and 15atomic-percent of nitrogen.
 6. The selector device of claim 1, whereinthe selector material includes Ge_(x)Te_(y)S_(1-x-y).
 7. The selectordevice of claim 1, wherein the selector material has a thickness between2 nanometers and 80 nanometers.
 8. The selector device of claim 1,wherein the selector material includes sulfur and tellurium and has anatomic ratio of sulfur to tellurium that is greater than
 1. 9. Theselector device of claim 1, wherein the selector device has a thresholdvoltage that is less than 1 volt.
 10. The selector device of claim 1,wherein the selector material includes less than 50 atomic-percent ofgermanium.
 11. A memory array, comprising: a memory cell, including astorage element and a selector device coupled to the storage element,wherein the selector device includes a selector material, the selectormaterial having a glass transition temperature that is greater than 350degrees Celsius.
 12. The memory array of claim 11, wherein the selectordevice includes a first electrode and a second electrode, the selectormaterial is between the first electrode and the second electrode, andthe first electrode or the second electrode is also an electrode of thestorage element.
 13. The memory array of claim 11, wherein the selectormaterial further includes a dopant.
 14. The memory array of claim 11,wherein the memory array includes a plurality of memory cells.
 15. Thememory array of claim 14, wherein the plurality of memory cells isarranged in multiple decks of memory cells.
 16. The memory array ofclaim 11, wherein the storage element is a resistive random accessmemory (RRAM) device, a phase change memory (PCM) device, or aspin-transfer torque magnetic random access memory (STT-MRAM) device.17. The memory array of claim 11, wherein the memory cell includes afirst terminal coupled to a bit line, and the memory cell includes asecond terminal coupled to a word line. 18-20. (canceled)
 21. Acomputing device, comprising: a circuit board; and a die communicativelycoupled to the circuit board, wherein the die includes a memory array,the memory array includes a memory cell having a storage element coupledin series with a selector device, the selector device includes aselector material, and the selector material has a glass transitiontemperature that is greater than 350 degrees Celsius.
 22. The computingdevice of claim 21, wherein the selector material includes less than 50atomic-percent of germanium.
 23. The computing device of claim 21,wherein the selector material has an atomic ratio of sulfur to telluriumthat is greater than
 1. 24. (canceled)
 25. (canceled)